The present invention relates in general to digital timing circuits and, more particularly, to controlling the phase of a data transfer signal to set the proper timing for reading or writing to a data register.
Parallel-serial converters are commonly used in digital circuit design to convert multi-bit signals to a string of data bits that are serially transmitted one at a time. Serial-parallel converters in turn convert the string of data bits back to multi-bit signals. In both applications, a data register is typically embedded within an integrated circuit that periodically receives new data sourced by external logic, or sources new data for external logic. Timing generation logic for reading or writing the data register is also embedded within the integrated circuit. The timing generation logic asserts a periodic signal to the external logic requesting data be presented to or removed from the data register.
Many applications involve high speed operation, say in the gigahertz range. The data transaction must be completed within a predetermined time period. That is, write data must be present and valid for a setup time before, and hold time after it is loaded into the register by a clock signal. Likewise, read data must be present and valid for a setup time before, and hold time after it is read by external logic. Unfortunately at such high data rates, the propagation delay uncertainties of the external logic are almost as long as the entire transaction period.
When the periodic signal is asserted to the external logic, requesting that new data be read or written, the external logic begins the time-consuming process of retrieving or storing new data. In the case of a request from the IC to the external logic to write new data, when the external logic finally presents new data to the integrated circuit, the new data typically propagates through buffer logic and eventually reaches the data register. The internal timing generation logic asserts a clock signal to load the data register. When the data transaction is so fast that propagation delay uncertainties consume almost the entire time period, there is no assurance that data arrives at the data register within register setup and hold-time constraints.
Since the write data register and timing logic are embedded within the integrated circuit, it is difficult to directly measure the actual write setup and hold-time. That is, the setup and hold-time are not readily observable by the external logic. If the write data setup and hold-time are unknown, the data rate of the external sourcing logic must be reduced to ensure sufficient setup and hold-time. Otherwise, where the propagation time uncertainty consumes a large portion of the transaction time period, the data transaction may fail to correctly time the data transfer under a worst-case timing analysis.
Hence, a need exists to properly set the timing of requesting more write data or read data for the data register to achieve maximum data transfer.